1. Field of the Invention
The present invention relates to an electrically programmable and erasable nonvolatile storage device and, more particularly, to techniques for verifying and correcting cell data stored in the nonvolatile storage device.
2. Description of the Related Art
An electrically programmable and erasable nonvolatile semiconductor storage device is called a flash memory which generally has a verifying function of cell data. In general, the verifying function includes the following functions: a first function of verifying whether program data has been correctly written in a memory and, if incorrect data exists, correcting the incorrect data; and a second function of verifying whether a memory has been erased normally in the case of erasing the memory cell and, if there is a memory cell which has not been erased, erasing this memory cell again. Both operations of these verifying functions are basically similar. The outline of the verifying function will be explained below.
FIG. 1 shows a verification circuit of a conventional non-volatile memory which has been described in Japanese Patent Application Laid-open Publication No. 3-286497, for example. Input program data is latched in a data latch circuit 11 and is then output to a data comparator 12 and a memory cell array 13 according to a designated address. The written data is read out by a sense amplifier (SA) 14 and is compared with the input program data by the data comparator 12. The comparison result is output as a verification result to a controller 15. The controller 15 resets the data latch circuit 11 depending on the verification result.
More specifically, the conventional non-volatile memory is provided with the data latch circuit 11 which is used to perform an erase-verification function or a write-verification function. In the case of the erase-verification function, all memory cells are subjected to the erase verification after the erasing operation has been completed. If at least one cell has not been completely erased, all memory cells are repeatedly subjected to the erase operation until all cells are normally erased.
In the case of the write-verification function, similar verification operations are performed as described in Japanese Patent Application Laid-open Publication No. 4-82090. More specifically, after writing data onto selected cells, data is read out from the selected cells and is then compared with latched data. If they do not match, the data is written onto the selected cells again.
As explained above, according to the conventional memory devices, a voltage supply circuit needs to supply a write/erase voltage to all the memory cells or all selected cells into which data are written at one time. Since all the memory cells or all the selected cells may include cells into which data has been normally written, the voltage supply circuit is burdened with a load larger than necessary.
Further, in the program operation, a higher voltage is applied to memory cells than at the time of reading. Therefore, an excessive writing operation, that is, a writing operation of data in a correctly written memory cell again, becomes a cause of generating a stress to the memory cell. Further, since the verifying operation in the case of the erasing of a memory cell is also carried out in the same circuit structure, this problem also applies to the erasing of memory cells. In the nonvolatile semiconductor storage device described in Japanese Patent Application Laid-open Publication No. 3-286497, a decision of whether a latch circuit is to be reset or not is made based on a result of a verification. However, as a resetting is carried out for the whole bits at one time, this nonvolatile semiconductor storage device also has a similar problem to the above.